From: Laurent MAZET <laurent.mazet@thalesgroup.com>
Date: Mon, 20 Oct 2025 13:26:08 +0000 (+0200)
Subject: adapt instruction block length to cache size
X-Git-Url: https://secure.softndesign.org/git/?a=commitdiff_plain;h=46b0d7b85c50837420ead7433b71c0691279c269;p=benchmarks.git

adapt instruction block length to cache size
---

diff --git a/load.c b/load.c
index 15b734b..4554122 100644
--- a/load.c
+++ b/load.c
@@ -204,18 +204,6 @@ double estimate_cpu_clock (void)
               INST2 INST2 INST2 INST2  INST2 INST2 INST2 INST2
         asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
         asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
-        asm volatile (INST3 : [i] "+r" (instructions) :: "cc");
     }
 
     struct timeval tv2;